1. Field of the Invention
This invention relates to a semiconductor integrated circuit device where multiple chips are mounted in the same package and a test method for that semiconductor integrated circuit device.
This application has foreign priority benefits of Japanese Patent Application No. 2007-336421 having a Japanese filing date of Dec. 27, 2007.
2. Description of Related Art
Semiconductor integrated circuit devices for large scale systems are being planned that utilize the SiP (System in Package) structure where a mixture of chips with multiple different functions such as memory chips and logic chips are mounted in one package. In semiconductor integrated circuit devices using the SiP structure however there is a limit on the number of input/output terminals that can be installed on the package due to ever smaller package sizes and demands to reduce the number of pins. So on an increasing number of packages there are no input/output terminals for external direct access to the memory chip. However making memory tests after assembling the package is impossible unless there is an external output from the memory terminals. One way to avoid this problem is a method that tests the memory chip via the logic chip.
FIG. 10 is a block diagram showing a semiconductor integrated circuit device with SiP structure of a related art for testing the memory chip by way of the logic chip (patent document 1). This semiconductor integrated circuit device of the background art contains a logic chip 502 and a memory chip 503 on an organic substrate (interposer).
The logic chip 502 internally contains a test processor circuit 505 and an internal circuit 504. This memory chip 503 is structured to input and output data in reply to the access requests made via the logic chip 502, and does not directly connect to the external terminals on the SiP (package) 501.
As shown in FIG. 10, the test processor circuit 505 contains a test circuit 521, and a high-speed test control circuit 522. The high-speed control circuit 522 on SiP 501 connects to the access terminals on the memory chip 503 by way of the test circuit 521, controls the read and write operation on the memory chip 503 from the external terminals 523n, and also tests the memory chip 503 by monitoring the read data. This high-speed test control circuit 522 is capable of selecting the signal transfer rate between the external terminal 523n and the memory chip 503 according to the data speed.
FIG. 11 shows a portion of the block diagram of test processor circuit 505. The high-speed test control circuit 522 connects to the external terminal 523n as was already described. The signal A is then input by way of the external terminal 523n. This signal A is input by way of a buffer 531 to one of the input terminals of the AND gate 542.
The output signal from this AND gate 542 connects directly to one of the input terminals on the selector 551, and the output from a high-speed test adjuster circuit 547 is input to the other input terminal. During low-speed test mode, the selector 551 selects the output signal from the AND gate 542; and during high-speed test mode selects the output signal from the high-speed test adjuster circuit 547.
Moreover, the selector 551 supplies an output signal to one of the input terminals on the selector 554, and the internal circuit 504 inputs a signal to the other input terminal on the selector 554. During test mode, the selector 551 output signal is selected, and during the actual operation mode the signal from the internal circuit 504 is selected and output. The output signal from this selector 554 is output by way of a buffer 560 as the signal B, to the memory chip 503.
The memory chip 503 supplies the signal B by way of the buffer 559 to one input terminal of the AND gate 550, and this signal B connects to the internal circuit 504. The output signal from the AND gate 550 is supplied to one of the input terminals on the selector 539, and the output signal from a high-speed test adjuster circuit 546 is supplied to the other input terminal. During low-speed test mode the selector 539 selects the output signal from the AND gate 550; and during high-speed test mode selects the output signal from the high-speed test adjuster circuit 546.
Moreover, the selector 539 output signal is supplied to one of the input terminals on the selector 537; and a user mode signal from the internal circuit 504 is supplied to the other input terminal. During test mode the output from the selector 539 is selected; and during actual operation mode the user mode signal from the internal circuit 504 is selected and output. The output from the selector 537 is output via the buffer 530 from the test terminal 5231.
The high-speed test adjuster circuit contains multiple retiming flip-flops. These flip-flops can suppress variations in the delay time that were caused by fluctuations in device characteristics. High speed signals can in this way propagate across long distances.
Patent documents 2 and 3 described in the problem to be solved by the Invention disclose semiconductor integrated circuit devices for directly monitoring the analog level.    [Patent document 1] Japanese Patent Application Laid Open No. 2007-255984, FIG. 1 through 3, Paragraphs 0022-0038    [Patent document 2] Japanese Patent Application Laid Open No. Hei5 (1993)-232188    [Patent document 3] Japanese Patent Application Laid Open No. Hei6 (1994)-69308